Please note that you are NOT allowed to reproduce any of this page elsewhere on the Web without my permission.
<<Click here to find out how to build your own ZX80>>
<NEWER VERSION EXISTS. PLEASE CLICK HERE TO SEE LATEST VERSION>
The circuit presented here is designed to be an add-on to the ZX80 circuit described on my ZX80 home page. Adding this to the ZX80 circuit and using the ZX81 ROM will allow you to build a FULLY FUNCTIONING ZX81 USING DISCRETE TTL.
<PREVIOUS VERSION (ZX80 timing) CAN BE FOUND HERE>
by Grant Searle
Last update: 31st July 2011
The design of this circuit provides the ZX80 circuit with full ZX81 compatibility for both SLOW and FAST modes
To allow the ZX80 circuit to become a fully compatible ZX81, two modifications are required:
1. Replace the 4K ZX80 ROM with an 8K ZX81 ROM.
2. Add some hardware to ensure the screen is properly refreshed during program execution. The complete conversion (including white-level restoration) is accomplished using 5 ICs and a small number of other components.
In slow mode, the screen is processed as follows:
1. Vertical sync, performed using software.
2. The blank part above the display. The processor is executing the user program at this stage, so additional hardware is used to create the sync signals to keep the video display locked. NMI pulses need to be generated to allow the ZX81 ROM keep track of the number of lines that have been drawn on the screen. to know when to start the character display.
3. The actual screen display. The processor is now back in control of the display and is used to create the sync signals and the actual character display.
4. The blank part below the display. Again, the additional hardware is switched back into use to allow the sync signals to be created while the processor executes the programs. Again, NMI pulses need to be generated to allow the ZX81 ROM keep track of the number of lines that have been drawn on the screen to know when to generate the VSYNC pulse.
The previous version worked using ZX80 timings for the sync (20 cycles wide) and would inject syncs during the NMI active time. This worked properly for most software, but had small issues with the display when using ZX81 "pseudo high res" software, because the original display routine was replaced with another which had different timing assumptions (due to working on a ZX81).
This version now replaces the HSYNC signals for the complete display, and they remain locked in a 207 cycle timing loop. These are re-synchronised every VSYNC signal. This part of the circuit is very similar to other ZX81 replacement circuits on the net, and uses a sync timing of 15 cycles.
The reason for this is that the 15 cycle sync is that it is easy to implement. To do the 16 sync ZX81 timing required more gates and offered no functional difference (none of the SYNC timings on the ZX80 or ZX81 were accurate, anyway!). The 15 cycle count actually produces a sync pulse more accurate than the ZX81 16 cycle count.
Due to the VSYNC signal holding the reset on the counter active, it does not start counting until VSYNC is de-activated (goes low). Counting then starts, and the first HSYNC after the VSYNC signal occurs when the counter reaches 192.
Here is the circuit which can be used to create these sync signals (with optional white-level restoration)...
Note: IC U5:D, IC U5:C, D2, R2 and C2 are not needed for converting the
ZX80 to a ZX81 but I would recommend doing so to allow the video to be displayed
correctly on a TV screen without the need to turn up the brightness. This part
of the circuit can also be used without the rest of the NMI hardware on the
original ZX80 circuit to improve the ZX80 video.
Switch positions shown are for the normal NMI sync active status (ie. normal operation) and are not needed if only ZX81 operation is required.
Switch 1 will enable or disable the NMI circuit. This needs to be set to the ground connection when running the ZX80 rom.
Switch 2 will select between the new sync signals or the original ZX80 sync signals. Normally this can remain on the new sync signal. The only exception is when running some of the ZX80 "flicker free" games which generate their own syncs that don't correspond with the normal timing between the VSYNC and HSYNC. In this case, the screen will not be centred unless the switch is on the old ZX80 sync position.
It is during the blank areas that the programs can run. During these periods no HSYNC pulses are generated by the ZX80. These need to be generated by this hardware to ensure the complete picture is correctly displayed. After a certain number of generated NMI / HSYNCs, the ROM code turns off the NMI generator and the normal display routine is called. The display routine will actually generate the HSYNC signals. However, this circuit replaces the complete HSYNC output, so the software generated HSYNCS are filtered to ensure they to not reset the counter circuitry. At the end of the character display the ROM turns the NMI generator back on and the program in memory can resume running. Again, during this period the program is once again interrupted by the NMIs to allow the ROM to keep track on the number of lines at the bottom of the display and the hardware will generate the HSYNC pulses. Once a number of pulses have been generated, the NMIs are again turned off and the CPU executes the ROM routine for scanning the keyboard and producing the VSYNC pulse. The above procedure cycles to produce a continuous display.
The sync generator part of circuit can be split into several defined areas:
1. The free-running sync generator, creating a pulse of 15 cycles every 207 cycles. Any deviation to this during the display will result in the monitor temporarily losing the lock on the SYNC signal, and the display will no longer remain vertically aligned.
2. The WAIT circuit, to resynchronise the processor to the start of the processor cycle.
3. The NMI on/off latch. The NMI pulses are enabled by an OUT FE,A and disabled by an OUT FD,A.
4. The SYNC mixer - the filtered VSYNC signals (from the ZX80 hardware) are mixed with the hardware generated HSYNC signals to produce the composite sync output.
5. ZX80 video hardware disable during the NMI active parts.
A simple free-running counter, clocked by the /phi signal at 3.5MHz from the ZX80 clock. Reset occurs when the counter reaches 207. Reset will also occur when a (filtered) VSYNC signal is detected, ensuring the signal remains synchronised when the ZX80/ZX81 code is running in "FAST" mode.
HSYNC generator runs in a 207 cycle loop, counting from 0 to 206. When 207 is
reached, the counter reset logic is activated causing an immediate reset to 0.
When the count is showing 192,193,194...206, (ie. 15 cycles at the top of the count), the HSYNC gate output is active. So, the output of this part of a circuit is a positive pulse, 15 cycles (4.6uS) in duration every 207 cycles (63.7uS).
Video logic disable and Sync logic disable
During the NMI active parts of the screen, the ZX80/ZX81
hardware can run any software. Some of the software operation could (and does)
interfere with the display circuitry, due to limited hardware decoding. To
avoid this, the appropriate parts of the ZX80 circuitry (the video generation
and the sync generation) are disabled when the NMI latch is active. This
prevents any glitches appearing on the screen and prevents accidental VSYNCs
The Video logic disable is really equivalent to an "AND" gate. A real gate would have been (and can be) used, but this would mean that I required a further chip. The arrangement that I have shown in the circuit works perfectly so I didn't see any need to add an extra chip for a single gate.
The counter must only be reset when VSYNCs occur. However,
some software will use the same circuitry to generate their own syncs. These
are filtered out using an R/C filter - the output will become active only if
the input has been active for more than a certain period. The values in this
circuit are roughly about half a line scan, so short pulses used for HSYNCS
are removed, but the VSYNC signal will pass through (after being active for
approx half a line, anyway). This will result in the VSYNC being slightly
shorter than originally generated, but this is not a problem as the original
VSYNCs are normally much too long, anyway, and the monitors will not have any
problem with the slightly shortened VSYNC. Only the start of the VSYNC is
affeced. The end (and the important) part remains the same.
Logic low on the input quickly discharges the capacitor via the diode. When a logic high appears, the capacitor takes time to charge via the resistor. Only if the input is held high for long enough will the capacitor voltage be sufficient to activate the output.
White level restoration (back porch generation)
The back-porch is an important part of the video signal which is used
(among others) to set the black-level of the video signal. When a "black on
white" display is being displayed, the lack of this being correctly set results
in the whole display being dark, which is why you need to turn the brightness
up. When using "white on black", the start of the line is dark, so the video is
correctly displayed with the dark level being correctly sampled. This can
be easily cured, and is shown on the bottom-right of the circuit.
My circuit stretches the sync pulse and uses this stretched pulse to inhibit the video output (ie. the video is at the black level) for a short duration after the sync pulse. This "back porch" period is then sampled by the monitor/television to correctly determine the black level in the video signal, so the white background appears at the correct intensity.
This is the same as used in the ZX81 production model, and is a simple gate implemented using a transistor and a couple of other components. The intention is to ensure the CPU is at the correct T-State every time the NMI signal is activated.
/WAIT will be pulled low if the /HALT is high and /NMI is low.
This could also be implemented using normal logic gates if prefered.
No resetting of the flip-flops is required since the first instruction issued by the ZX81 ROM is an OUT FD,A (turn off NMI).
A little note about the video
The CCIR definition for a 625 line video signal includes the following...
Each line has a 64uS duration,
giving a line frequency of 15.625kHz.
The blanking part of the line signal should be 12uS long, consisting of:
1.5uS front porch
4.7uS horizontal sync
5.8uS back porch
Needless to say, the ZX80 and ZX81's are a
bit off on ALL timings!
1 line is 207 cycles, giving a 63.69uS duration (15.701kHz frequency)
For the ZX80, each sync is 20 cycles long, giving a duration of 6.15uS
For the ZX81, each sync is 16 cycles long, giving a duration of 4.9uS (much closer than the ZX80)
There is no front porch (not important)
There is no back porch (except on the latest issue of the ZX81)
SAVEs and LOADs
This circuit will continually generate a steam of HSYNC signals. This would interfere with the "Mic" output, so the sync signals have now been split. The old sync generator on the ZX80 board is still connected to the Mic socket and the new sync signals are sent to the screen.
Here is the circuit described above constructed on
Most connections are made under the PCB. Others reach the isolated chip pins that have been bent out and soldered to. See later on in this page to see a closer view of the connections needed.
Construction would be straightforward and layout is not critical. A suggested layout would be to have all ICs in one line on a small board then attach it on top of some of the row of ICs that are just above the keyboard with some double-sided foam fixing pads.
This circuit is incorporated into the existing ZX80 circuit as follows:
/WAIT, /HALT, /NMI, A0, A1
These signals are taken from the Z80 CPU.
Taken from IC18 pin 8
/IORQ + /WR
Connected to IC17 pin 6
IC11 PIN 10, IC11 PIN 11 (The Sync logic disable)
The connection between IC11 Pin 10 and IC 11 Pin 11 is broken. This can be achieved by bending out pin 11 on IC11 and soldering the appropriate connection to the bent-out pin. The other connection can be attached directly to the underside of the ZX80 PCB.
IC13 PIN 10, IC16 PIN 10 (The video logic disable)
The connection between IC13 Pin 10 and IC 16 Pin 10 is broken. This can be achieved by bending out pin 10 on IC13 and soldering the appropriate connection to the bent-out pin. The other connection can be attached directly to the underside of the ZX80 PCB.
Connected to IC20 Pin 6
Lift the right-hand side of R30 from the ZX80 board and connect this line to the lifted leg of this resistor
OLD /SYNC IN
Connect to IC19 Pin 5 on the ZX80 board.
Lift the right-hand side of R32 from the ZX80 board. Bend out Pin 1 of IC21.
Connect the lifted leg of the resistor to the bent out pin on IC21 with a short length of wire. Then, connect this to the OLD /SYNC IN on the NMI board.
The following pictures illustrate the connections made to the top of the board, as described above:
SYNC OUT and VIDEO OUT:
Video and sync disable, chip pins bent out and soldered:
Connections for the back of the ZX80 board are shown here...
The 8K ZX81 ROM is required for SLOW-mode to work. NMIs will not work
with the ZX80 ROM - it will cause the ZX80 to crash. The 8K ROM requires
A12 from the Z80 to be taken to A12 on the ROM. /OE on the ROM is to be
Here is Manic Miner running on the hardware shown above,
using pseudo high-res graphics:
If you are using a ZX80 ROM, make sure the NMI switch is OFF before you power-up the machine, because the ZX80 ROM is not compatible with the NMI generation.
SOME OF MY OTHER PAGES
own ZX80 - my page showing
you how to build this old micro
|__ ZX80 to ZX81 conversion - build the NMI generator needed to convert the ZX80 circuit into a ZX81
|__ ZX80 software - Type in a Space Invaders game into the ZX80
Build your own Jupiter Ace - my page showing
you how to build this old micro
Build your own UK101 - my page showing you how to build a greatly simplified version of this old micro
Pong - Pictures of my build of the Atari classic arcade game
My Machines - My collection of classic 80's micros
To contact me, my current eMail address can be found here. Please note that this address may change to avoid spam.