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The circuit presented here is designed to be an add-on to the ZX80 circuit described on my ZX80 home page. Adding this to the ZX80 circuit and using the ZX81 ROM will allow you to build a FULLY FUNCTIONING ZX81 USING DISCRETE TTL.
by Grant Searle
Last update: 16th July 2011
The design of this circuit provides the ZX80 circuit with full ZX81 compatibility for both SLOW and FAST modes
To allow the ZX80 circuit to become a fully compatible ZX81, two modifications are required:
1. Replace the 4K ZX80 ROM with an 8K ZX81 ROM.
2. Add some hardware to ensure the screen is properly refreshed during program execution. The complete conversion (including white-level restoration) is accomplished using 6 ICs and a small number of other components.
In slow mode, the screen is processed as follows:
1. Vertical sync, performed using software.
2. The blank part above the display. The processor is executing the user program at this stage, so additional hardware is used to create the sync signals to keep the video display locked. NMI pulses need to be generated to allow the ZX81 ROM keep track of the number of lines that have been drawn on the screen. to know when to start the character display.
3. The actual screen display. The processor is now back in control of the display and is used to create the sync signals and the actual character display.
4. The blank part below the display. Again, the additional hardware is switched back into use to allow the sync signals to be created while the processor executes the programs. Again, NMI pulses need to be generated to allow the ZX81 ROM keep track of the number of lines that have been drawn on the screen to know when to generate the VSYNC pulse.
The existing ZX80 hardware will generate horizontal SYNC pulses that are 20 cycles
wide, at a period or 207 cycles. To ensure that the NMI hardware sync switchover
produces a stable display, the sync must continue through the display at
precisely the same timings.
So, the hardware for the SYNC pulses must have a steady stream of pulses 20 cycles wide.
The ZX81 ULA produces sync pulses of 16 cycles width, and the NMI circuit within the ULA uses this 16 cycle pulse for the CPU NMI. Due to the 20 cycle ZX80 hardware sync pulse generation, it is not possible for the ZX80 NMI adapter to use the NMI pulse directly to generate the SYNC. As a result, the NMI generator here actually needs to generate two streams of pulses.
A 16 cycle pulse for the NMI, repeated every 207 cycles.
A 20 cycle pulse for the SYNC, repeated every 207 cycles.
Due to the ZX80 and ZX81 circuitry having different ways of generating the start of the SYNC pulse (and the ZX81 ROM therefore assuming different SYNC timings what is actually produced by the ZX80 circuit), the two pulses actually need to be offset from one another.
The real timings for a ZX80 and ZX81 sync generation are shown here...
The IORQ low signal is actually an "INTACK" (as /M1 is low).
The ZX81 sync and NMI are the same timing.
As you can see, the ZX80 sync actually occurs 3 cycles earlier than would be generated by a ZX81. So, I actually needed to generate the the start of the SYNC pulse 3 cycles earlier than the NMI. This is illustrated below:
Failure to offset the pulses would mean that the switchover of sync pulses
from this circuit to the software triggered ZX80 sync circuit for the first line of the
active display part of the screen would appear 3 cycles too early, causing a
major disruption to the top line of the display.
The numbers in bold in the above graph are the important ones that I need to use to switch the signals.
So, here is a circuit which can be used to create these missing sync signals (with optional white-level restoration)...
Note: IC U6:C, IC U6:D, D2, R2 and C2 are not needed for converting the ZX80 to a ZX81 but I would recommend doing so to allow the video to be displayed correctly on a TV screen without the need to turn up the brightness. This part of the circuit can also be used without the rest of the NMI hardware on the original ZX80 circuit to improve the ZX80 video.
It is during the blank areas that the programs can run. During these periods the HSYNC pulses required for a stable TV display are generated and NMI pulses are generated to allow the ZX80 ROM to keep track of the number of lines drawn on the screen and to synchronise the processing to ensure a clean switchover between the hardware generated and software triggered pulses. Once a number of NMIs (and therefore HSYNCS) have been generated the ROM turns the NMI generator off and the CPU enters the ROM routine for producing the display. During this time the HSYNCS are produced by the existing ZX80 hardware, and are triggered under software control. At the end of the character display the ROM turns the NMI generator back on and the program in memory can resume running. Again, during this period the program is once again interrupted by the NMIs to allow the ROM to keep track on the number of lines at the bottom of the display and the hardware will generate the HSYNC pulses. Once a number of pulses have been generated, the NMIs are again turned off and the CPU executes the ROM routine for scanning the keyboard and producing the VSYNC pulse. The above procedure cycles to produce a continuous display.
The sync generator part of circuit can be split into several defined areas:
1. The free-running sync generator, creating a pulse of 20 cycles every 207 cycles. These values are chosen to EXACTLY match the syncs produced by the ZX81 ROM when the character part of the display is being drawn. Any mismatch will result in the monitor temporarily losing the lock on the SYNC signal, and the display will slant.
2. The WAIT circuit, to resynchronise the processor to the start of the processor cycle.
3. The NMI on/off latch. The NMI pulses are enabled by an OUT FE,A and disabled by an OUT FD,A.
4. The SYNC mixer - here, the software triggered SYNCS are passed through when the NMI is off and the hardware-generated syncs are passed through when the NMI is on. Gating ensures only the correct signals are passed through.
Horizontal pulses during the non-character display part of the TV frame are produced by the NMI generator. As a result, this generator must duplicate the line frequency of the TV signal precisely. The ZX80 produces a pulse lasting 20 clock cycles @ 3.25MHz (giving a duration of 6.15uS). This pulse is produced at 207 clock cycle intervals (giving one pulse every 63.69uS).
Once the last NMI has been received for the top part of the display, the ZX81 ROM routine will take over and display the main part of the screen using software triggered HSYNC pulses. However, the ZX80 circuit generates the HSYNC pulses differently to the ZX81 ULA. This will result in the time between the start of the last NMI generated HSYNC and the start of the first ROM triggered HSYNC to be 204 cycles, instead of 207 cycles if the start of the SYNC occurred at the same time as the start of the NMI. This is why the NMI generator SYNCS actually appear 3 cycles earlier than the NMI signals.
Character line count reset
During the hardware generated video part of the screen, the CPU runs the software. However, this can cause the character line reset to become active at various times so when the characters are then displayed (during the software display part of the screen refresh) the top line of the character is not always zero as it may have been reset at any time during the blank part of the screen. This count is automatically updated for every SYNC pulse and should always be zero when the top line of the character is displayed. The effect of this is that you would sometimes get random jumps (actually a roll) in the characters when programs are being executed.
This is solved by disabling the character line count reset circuitry during the NMI-active (ie. hardware generated) parts of the screen.
Spurious sync removal
While the NMI is ON, the HSYNC signals passed to the video output must be from the NMI generator only as spurious HSYNC signals are produced by the ZX80 circuit when programs performing I/O are run. During the character display, the NMI is off so the pulses are obtained from the existing ZX80 HSYNC circuit and the hardware generated SYNC pulses are blocked.
A small problem exists here. When an OUT FD,A is issued (to turn off the NMI) an additional spurious HSYNC pulse is generated by the ZX80 circuit. This is due to a limitation in the original ZX80 design where IORQ will generate a pulse if the SYNC is currently high. My circuit suppresses the ZX80 sync pulses when the NMI generator is enabled. When the NMI is turned off, I stretch the "NMI ON" signal slightly to cover this glitch, This will prevent a black line appearing just above the top character on the TV display (and the character line count being incorrectly incremented).
Exact sync matching (optional)
The generator shown here uses the CPU clock as the source. However, the existing ZX80 sync generator uses the "M1" signal to clock the edges of the sync pulse. The M1 signal on the Z80 very slightly lags behind the clock signal. So, the syncs generated by this circuit (if not compensated) would be very slightly ahead of the equivalent ZX80 hardware generated syncs. This causes a VERY MINOR slant in the top line of the displayed characters, as the TV resynchronises to the scan lines. To exactly align the syncs, a suitable delay needs to be created. This is achieved by adding a resistor+capacitor between the SYNC output of the clock generator and the input of the SYNC mixer. This causes a small slope to be introduced in the pulse. This slope means that there is a small delay before the input of the SYNC mixer gate reaches the switching voltage. This delay allows the SYNCS to be matched.
This sync correction circuitry may not needed if you cannot notice the slope error.
White level restoration (back porch generation)
The back-porch is an important part of the video signal which is used
(among others) to set the black-level of the video signal. When a "black on
white" display is being displayed, the lack of this being correctly set results
in the whole display being dark, which is why you need to turn the brightness
up. When using "white on black", the start of the line is dark, so the video is
correctly displayed with the dark level being correctly sampled. This can
be easily cured, and is shown on the bottom-right of the circuit.
My circuit stretches the sync pulse and uses this stretched pulse to inhibit the video output (ie. the video is at the black level) for a short duration after the sync pulse. This "back porch" period is then sampled by the monitor/television to correctly determine the black level in the video signal, so the white background appears at the correct intensity.
This is the same as used in the ZX81 production model, and is a simple gate implemented using a transistor and a couple of other components. The intention is to ensure the CPU is at the correct T-State every time the NMI signal is activated.
/WAIT will be pulled low if the /HALT is high and /NMI is low.
This could also be implemented using normal logic gates if prefered.
No resetting of the flip-flops is required since the first instruction issued by the ZX81 ROM is an OUT FD,A (turn off NMI).
A little note about the video
The CCIR definition for a 625 line video signal includes the following...
Each line has a 64uS duration,
giving a line frequency of 15.625kHz.
The blanking part of the line signal should be 12uS long, consisting of:
1.5uS front porch
4.7uS horizontal sync
5.8uS back porch
Needless to say, the ZX80 and ZX81's are a
bit off on ALL timings!
1 line is 207 cycles, giving a 63.69uS duration (15.701kHz frequency)
For the ZX80, each sync is 20 cycles long, giving a duration of 6.15uS
For the ZX81, each sync is 16 cycles long, giving a duration of 4.9uS (much closer than the ZX80)
There is no front porch (not important)
There is no back porch (except on the latest issue of the ZX81)
SAVEs and LOADs
Please note that this circuit correctly handles saving (which is shared with the SYNC generation on the ZX80 and ZX81) because the ZX81 will turn off the NMI while the SAVE is being performed, and this circuit will correctly pass-through the pulses required when writing to tape (NMI off).
Here is the circuit described above constructed on
Most connections are made under the PCB. Others pass through the mounting hole on the board to reach the isolated chip pins that have been bent out and soldered to. See later on in this page to see a closer view of the connections needed.
Construction would be straightforward and layout is not critical. A suggested layout would be to have all ICs in one line on a small board then attach it on top of some of the row of ICs that are just above the keyboard with some double-sided foam fixing pads.
This circuit is incorporated into the existing ZX80 circuit as follows (bold letters refer to my circuit, any other numbers refer to the original ZX80 circuit):
/WAIT, /HALT, /NMI, A0 and A1 signals are taken from the Z80 CPU.
/PHI is taken from IC18 pin 8
IORQ+WR is connected to IC17 pin 6
The connection between IC19 pin 5/IC 18 pin 1 and IC21 pin 1/R32/R35 is to be broken
and the following connections made:
SYNC IN is taken from IC19 pin 5/IC 18 pin 1
SYNC OUT is connected to IC21 pin 1/R32/R35.
The connection to IC21 pin 3 needs to be
/RST DISABLE connects to IC21 pin 3
If the white-level restoration is
to be included then the connection from the video out
to the modulator (between IC9 and R30) is to be broken and the following
VIDEO IN is taken from IC20 pin 6
VIDEO OUT is connected to R30
The 8K ZX81 ROM is required for SLOW-mode to work. NMIs will not work
with the ZX80 ROM - it will cause the ZX80 to crash. The 8K ROM requires
A12 from the Z80 to be taken to A12 on the ROM. /OE on the ROM is to be
Below are the connections required to add the prototype NMI circuit to the ZX80 board described on my other page.
Connections for the back of the ZX80 board are shown here...
The top level changes require the chip pins to be bent out so
that they do not connect to the socket.
Here, IC21 Pin 3, IC19 pin 5, IC18 Pin 1 and IC20 pin 6 are bent out and soldered to.
IC19 pin 5 and IC18 pin 1 are connected together by a short wire (as these were previously connected together via the PCB tracks).
These pins are then soldered to and passed to the NMI circuitry...
If you are using a ZX80 ROM, make sure the NMI switch is OFF before you power-up the machine, because the ZX80 ROM is not compatible with the NMI generation.
MY OTHER PAGES
own ZX80 - my page showing
you how to build this old micro
|__ ZX80 to ZX81 conversion - build the NMI generator needed to convert the ZX80 circuit into a ZX81
|__ ZX80 software - Type in a Space Invaders game into the ZX80
Build your own Jupiter Ace - my page showing
you how to build this old micro
Build your own UK101 - my page showing you how to build a greatly simplified version of this old micro
Pong - Pictures of my build of the Atari classic arcade game
My Machines - My collection of classic 80's micros
To contact me, my current eMail address can be found here. Please note that this address may change to avoid spam.