Converting the ZX80 into a ZX81 (Slow-mode NMI/Sync generation)
...on-line since March 1997 !

Please note that you are NOT allowed to reproduce any of this page elsewhere on the Web without my permission.

<<Click here to find out how to build your own ZX80>>

VERSION 4.1 (Exact ZX81 Sync timings, INTACK Synchronisation)

The circuit presented here is designed to be an add-on to the ZX80 circuit described on my ZX80 home page. Adding this to the ZX80 circuit and using the ZX81 ROM will allow you to build a FULLY FUNCTIONING ZX81 USING DISCRETE TTL.

<PREVIOUS VERSION (VSYNC synchronisation) CAN BE FOUND HERE>

by Grant Searle

Last update: 26th September 2011

Acknowlegements
This page contains a circuit designed by myself with a little help from others:
Doug Duchene for providing me with a scan of an old NMI generator schematic which helped me complete my old design) along with a circuit description. This schematic was for the "CES ZX80 Video Upgrade".
Wilf Rigter for details of IN and OUT port numbers, and information on the working of the ZX81 display routines.
The T-state synchroniser part is taken from Sinclair's ZX81 schematic.

Based on the help mentioned above, I then recreated the complete design.

Changes log:
* March 1997 - NMI (ZX81) conversion added to the Web
* 31st Aug 2011 - Version 4 released here
* 17th Sep 2011 - Version 4.1 - small update to allow NMI board enabling via an input pin instead of a switch
* 26th Sep 2011 - Version 4.1 soldered and attached to the ZX80. Construction details below.

CONTENTS  

 Overview
 The Circuit
 Circuit Operation
 Prototype
 Connections
 Suggested construction
 Powering Up
 Hardware Verification
 Some of my other pages
 


OVERVIEW

The design of this circuit provides the ZX80 circuit with full ZX81 compatibility for both SLOW and FAST modes

To allow the ZX80 circuit to become a fully compatible ZX81, two modifications are required:

1. Replace the 4K ZX80 ROM with an 8K ZX81 ROM.
2. Add some hardware to ensure the screen is properly refreshed during program execution. The complete conversion (including white-level restoration) is accomplished using six ICs and a small number of other components.

 


THE CIRCUIT

The additional hardware is required to create the video sync signals while the ZX81 is executing the program. On the ZX80 (and ZX81 Fast mode), the screen display is lost because the processor is no longer being used to create the video signal.

In slow mode, the screen is processed as follows:

1. Vertical sync, performed using software.
2. The blank part above the display. The processor is executing the user program at this stage, so additional hardware is used to create the sync signals to keep the video display locked. NMI pulses need to be generated to allow the ZX81 ROM keep track of the number of lines that have been drawn on the screen. to know when to start the character display.
3. The actual screen display. The processor is now back in control of the display and is used to create the sync signals and the actual character display.
4. The blank part below the display. Again, the additional hardware is switched back into use to allow the sync signals to be created while the processor executes the programs. Again, NMI pulses need to be generated to allow the ZX81 ROM keep track of the number of lines that have been drawn on the screen to know when to generate the VSYNC pulse.

The previous versions worked using either ZX80 timings for the sync (20 cycles wide) or a simplified sync timing (15 cycles wide) and would inject syncs during the NMI active time.

This version replaces the HSYNC signals for the complete display, and they remain locked in a 207 cycle timing loop. These are re-synchronised every INTACK signal, as in a real ZX81.

The SYNC (and NMI) are generated 16 cycles after the INTACK and remain active for a further 16 cycles. This implementation exactly matches the SYNCS produced by a real ZX81.

Timings of the real ZX81 syncs (same as generated here) along with the original ZX80 sync timings are shown in this picture:

The /IORQ and /M1 are low at the same time, indicating an INTACK signal.
Syncs for the ZX81 and ZX80 occur within a few clock cycles of each other, so the ZX80 circuit, running the original ZX80 ROM can use this new sync generator with no noticeable difference in the display (NMI must be turned off if the ZX80 ROM is being used).
The original ZX80 sync used the /M1 as a trigger. The ZX81 uses the INTACK and CPU clock.

Here is the circuit which can be used to create these sync signals (with optional white-level restoration)...


Power connections to the IC's are implied, and not shown. Gates can be swapped as needed depending on PCB layout. Gate input pins can be exchanged if needed.

The transistor can be just about any general-purpose NPN transistor, and is not critical.

Note: IC U3:D, IC U5:B, D2, R2 and C2 are not needed for converting the ZX80 to a ZX81 but I would recommend doing so to allow the video to be displayed correctly on a TV screen without the need to turn up the brightness. This part of the circuit can also be used without the rest of the NMI hardware on the original ZX80 circuit to improve the ZX80 video.

NMI GEN ENABLE will enable or disable the NMI circuit. This needs to connected to the Gnd connection when running the ZX80 ROM, Vcc when running the ZX81 ROM normally, or Gnd when running the ZX81 ROM with no NMI support (fast only).

Although highly unlikely to be needed, the option to switch between the new syncs and the old ZX80 syncs (works with ZX80 mode ONLY) can be introduced, as shown in this modification to the above circuit...


Switch 2 will select between the new sync signals or the original ZX80 sync signals and would only be suitable for ZX80 ROM use (will not work if slow mode ZX81 is in use). Not really needed, so can be omitted. If fitted, then this can normally remain on the new sync signal.


CIRCUIT OPERATION

It is during the blank areas that the programs can run. During these periods no HSYNC pulses are generated by the ZX80. These need to be generated by this hardware to ensure the complete picture is correctly displayed. After a certain number of generated NMI / HSYNCs, the ROM code turns off the NMI generator and the normal display routine is called. The display routine enables interrupts, which will be triggered at the end of each line. The interrupt acknowledge will reset the counter and cause a HSYNC to be triggered 16 cycles later. As the NMI switch is off, the HSYNC signal does not also generate an NMI signal. At the end of the character display the ROM turns the NMI generator back on and the program in memory can resume running. Again, during this period the program is once again interrupted by the NMIs to allow the ROM to keep track on the number of lines at the bottom of the display and the hardware will generate the HSYNC and NMI pulses. Once a number of pulses have been generated, the NMIs are again turned off and the CPU executes the ROM routine for scanning the keyboard and producing the VSYNC pulse. The above procedure cycles to produce a continuous display.

The sync generator part of circuit can be split into several defined areas:
1. The free-running sync generator, creating a pulse of 16 cycles every 207 cycles. Any deviation to this during the display will result in the monitor temporarily losing the lock on the SYNC signal, and the display will no longer remain vertically aligned.

2. The WAIT circuit, to resynchronise the processor to the start of the processor cycle.

3. The NMI on/off latch. The NMI pulses are enabled by an OUT FE,A and disabled by an OUT FD,A.

4. The SYNC mixer - the VSYNC signals from the ZX80 hardware are mixed with the hardware generated HSYNC signals to produce the composite sync output.

5. ZX80 video hardware disable during the NMI active parts.

Clock generator

A simple free-running counter, clocked by the /phi signal at 3.5MHz from the ZX80 clock. Reset occurs when the counter reaches 207. Reset will also occur when an INTACK signal is detected (/M1 and /IORQ going low), ensuring the signal remains synchronised when the ZX80/ZX81 code is running in "FAST" mode.

HSYNC generation

The HSYNC generator runs in a 207 cycle loop, counting from 0 to 206. When 207 is reached, the counter reset logic is activated causing an immediate reset to 0.
When the count is showing 16..31, (ie. 16 cycles near the start of the count), the HSYNC gate output is active. So, the output of this part of a circuit is a positive pulse, 16 cycles (4.9uS) in duration every 207 cycles (63.7uS).

Video logic disable and Sync logic disable

During the NMI active parts of the screen, the ZX80/ZX81 hardware can run any software. Some of the software operation could (and does) interfere with the display circuitry, due to limited hardware decoding. To avoid this, the appropriate parts of the ZX80 circuitry (the video generation and the sync generation) are disabled when the NMI latch is active. This prevents any glitches appearing on the screen and prevents accidental VSYNCs being generated.

White level restoration (back porch generation)

The back-porch is an important part of the video signal which is used (among others) to set the black-level of the video signal. When a "black on white" display is being displayed, the lack of this being correctly set results in the whole display being dark, which is why you need to turn the brightness up. When using "white on black", the start of the line is dark, so the video is correctly displayed with the dark level being correctly sampled. This can be easily cured, and is shown on the bottom-right of the circuit.
My circuit stretches the sync pulse and uses this stretched pulse to inhibit the video output (ie. the video is at the black level) for a short duration after the sync pulse. This "back porch" period is then sampled by the monitor/television to correctly determine the black level in the video signal, so the white background appears at the correct intensity.

T-State synchroniser

This is the same as used in the ZX81 production model, and is a simple gate implemented using a transistor and a couple of other components. The intention is to ensure the CPU is at the correct T-State every time the NMI signal is activated.

/WAIT will be pulled low if the /HALT is high and /NMI is low.
This could also be implemented using normal logic gates if preferred.

Power-up reset

No resetting of the flip-flops is required since the first instruction issued by the ZX81 ROM is an OUT FD,A (turn off NMI).

A little note about the video

The CCIR definition for a 625 line video signal includes the following...

Each line has a 64uS duration, giving a line frequency of 15.625kHz.
The blanking part of the line signal should be 12uS long, consisting of:
    1.5uS front porch
    4.7uS horizontal sync
    5.8uS back porch

Needless to say, the ZX80 and ZX81's are a bit off on ALL timings!
ie.
    1 line is 207 cycles, giving a 63.69uS duration (15.701kHz frequency)
    For the ZX80, each sync is 20 cycles long, giving a duration of 6.15uS
    For the ZX81, each sync is 16 cycles long, giving a duration of 4.9uS (much closer than the ZX80)
    There is no front porch (not important)
    There is no back porch (except on the latest issue of the ZX81)

SAVEs and LOADs

This circuit will continually generate a steam of HSYNC signals. This would interfere with the "Mic" output, so the sync signals have now been split. The old sync generator on the ZX80 board is still connected to the Mic socket and the new sync signals are sent to the screen.

 


PROTOTYPE

Here is the circuit described above constructed on solderless breadboard.
Most connections are made under the PCB. Others reach the isolated chip pins that have been bent out and soldered to. See later on in this page to see a closer view of the connections needed.


Construction would be straightforward and layout is not critical. A suggested layout would be to have all ICs in one line on a small board then attach it on top of some of the row of ICs that are just above the keyboard with some double-sided foam fixing pads.

 


CONNECTIONS

Please refer to the existing ZX80 circuit when following these instructions.
Below are the connections required to add the prototype NMI circuit to the ZX80 board described on my other page.

This circuit is incorporated into the existing ZX80 circuit as follows:

/WAIT, /HALT, /NMI, A0, A1, /M1, /IORQ
These signals are taken from the Z80 CPU.

/PHI
Taken from IC18 pin 8.

/IORQ + /WR
Connected to IC17 pin 6.

NMI GEN ENABLE
This can either be connected to a SPDT switch, to allow it to be connected to either Vcc or Ground (must always be connected to Gnd when running the ZX80 ROM) or, if you have used a 16K EPROM on the ZX80 containing both images on there (ZX80 image in 0-4K, ZX81 image in 8-16K), then this can connect to the ZX80/ZX81 ROM selection address (A13) on the EPROM for automatic enabling for ZX81 and disabling for ZX80 running.

IC11 PIN 10, IC11 PIN 11 (The Sync logic disable)
The connection between IC11 Pin 10 and IC 11 Pin 11 is broken. This can be achieved by bending out pin 11 on IC11 and soldering the appropriate connection to the bent-out pin. The other connection can be attached directly to the underside of the ZX80 PCB.

IC5 PIN 9, IC16 PIN 10 (The video logic disable)
The connection between IC13 Pin 10 and IC 16 Pin 10 is broken. This can be achieved by bending out pin 10 on IC13. The connections can be attached directly to the underside of the ZX80 PCB.

VIDEO IN
Connected to IC20 Pin 6.

VIDEO OUT
Lift the right-hand side of R30 from the ZX80 board and connect this line to the lifted leg of this resistor.

OLD /SYNC IN * (shown on "optional" circuit)
Connect to IC19 Pin 5 on the ZX80 board. Unlikely to be needed, though, and can be omitted.

/SYNC OUT *
Lift the right-hand side of R32 from the ZX80 board. Bend out Pin 1 of IC21.
Connect the lifted leg of the resistor to the bent out pin on IC21 with a short length of wire. Then, connect this to the /SYNC OUT on the NMI board.

* - Alternative SYNC OUT (more "faithful" to the original ZX81 - HSYNC glitches present on "Save" Mic signal)
Instead of the above OLD /SYNC IN and SYNC OUT modifications shown above, do the following...
Bend out IC19, Pin 5. (Alternatively, remove IC19, as it is no longer needed).
Connect /SYNC OUT to the track connecting IC21 Pin 1, R32 and R35.
If OLD /SYNC IN is also needed, also bend out IC18 Pin 1, connect with a short wire to the bent-out pin 5 on IC19, then connect to the OLD /SYNC IN.

The following pictures illustrate the connections made to the top of the board, as described above:

SYNC OUT and VIDEO OUT:

Video and sync disable, chip pins bent out and soldered:

Connections for the back of the ZX80 board are shown here...

The 8K ZX81 ROM is required for SLOW-mode to work. NMIs will not work with the ZX80 ROM - it will cause the ZX80 to crash. The 8K ROM requires A12 from the Z80 to be taken to A12 on the ROM. /OE on the ROM is to be permanently grounded.
 


CONSTRUCTION

Layout is not critical and can be however you wish.
I wanted to keep the main ZX80 board as clear as possible, so I decided to construct it as a thin strip that can be mounted on the right hand side of the board, clear from the other components. Here are details of this construction.

The layout that I did on the breadboards was just about optimal for thin-strip layout, so I kept the same positioning.

This was constructed on "tri-pad" board, and using "Wire runner" wire (looks like enamelled copper wire, but the insulation melts when soldered with a VERY hot iron, allowing the wire to be soldered without needing to be stripped). All data inter-connections are on the back of the board. The power bus connecting Vcc to pin 14 or each IC and Gnd to pin 7 of each PC was made on the front of the board. This was done before the chip sockets were attached, and can be seen as two copper wires running under the chips, shown here:


(The board was trimmed later on, making it smaller. This can be seen in later pictures.)

Once soldered, I used some masking tape to label the pins (reversed on the back) to make sure connections were made to the correct pins:

The additional components were added and then, the "Wire runner" connections are made. These connections can be seen running along the middle of the board:

Top of the board with all components added. Some component leads share the same holes, as I wanted this as small as possible:

I wanted the bottom row of holes to drop below the ZX80 board level, and the rest of the components above the ZX80 board level. I then used the bottom row of holes to feed the ZX80 rear connection wires through to keep things tidy:

Some "Sticky fixers" were attached to the side of some of the sockets. The board is then bent up vertically and pressed against the edge of the ZX80 board, securing it in place.

Here is the back of the board, showing the NMI board mounted at 90 degrees to the main board, with the connections passing through the bottom row of holes and connecting to the relevant points on the ZX80. Some other connections passed through the top holes to connect to the points needed on the front of the ZX80. Wire-wrap wire was used for the connections to the board.

The lower connections:

Here is the completed board, mounted on the side of the ZX80. In addition, the ZX80/81 ROM adapter and the 16K RAM pack that I built can also been seen. This is now a fully functional ZX80 or ZX81. The ROM selection jumper at the top of the EPROM selects A13 between Gnd (ZX80 image) and Vcc (ZX81 image) is also connected to the "NMI GEN ENABLE" pin of the board so that it is enabled automatically when ZX81 mode is selected.


POWERING UP

On powering up the revised circuit should show, after a few seconds, the K cursor in the bottom left of the screen.
If the NMI GEN ENABLE connected to Vcc and a ZX81 ROM is used, the machine will power-up in "Slow" mode.
If the NMI GEN ENABLE is connected to Gnd and a ZX81 ROM is used, the machine will power-up in "Fast" mode.
This circuit is fully compatible with the SLOW and FAST modes used on the ZX81.

Here is Manic Miner running on the hardware shown above, using pseudo high-res graphics:

If you are using a ZX80 ROM, make sure the NMI GEN ENABLE is connected to Gnd before you power-up the machine, because the ZX80 ROM is not compatible with the NMI generation.


HARDWARE VERIFICATION

It is impossible to find the schematic of the internals of the original ZX81 ULA, but to ensure the circuit that I described above matches the real ZX81 implementation, I did some checking with a real ZX81.
Here are my findings...

1. The Sync generator is totally free-running (doesn't need interrupts etc. to make it continue).
This can be proven with a simple program...
; Disable interrupts
    DI
; Disable NMI generator
    LD A,0
    OUT ($FD),A
; Loop forever, preventing any other program operation
loop
    JR loop

With the interrupts and NMI gen disabled, if the sync generation was not free-running then the video output would stop. However, a continual HSYNC stream is produced (no VSYNC due to NMI disabled).

2. The Vertical Sync does NOT reset the sync generator counter.
Again, this can be proven with a small program...
; Disable interrupts
    DI
; Disable NMI generator
    LD A,0
    OUT ($FD),A
loop
; Activate and reset the VSYNC, then loop.
    IN A,($FE)
    OUT ($FF),A
    JR loop

If the VSYNC activation was to reset the HSYNC counter then the video output would be a constant stream of very short "VSYNC" pulses. However, when observing the output, and adjusting the scope timebase carefully, it can be seen that these VSYNC pulses are actually superimposed with the correctly timed HSYNC pulses, showing that the HSYNC counter is not affected by the VSYNCs.

3. The triggering of the sync pulse is only via the sync generator counter, and does not have a seperate triggering circuit (like the sync gen in the ZX80).

4. The sync generation is permanently on.
There are no instances while running the ZX81 that the HSYNC does not appear.

5. The sync counter reset ONLY occurs with an INTACK signal.
I have verified this a while ago, and the HSYNC will only be re-synchronised when /M1 and /IORQ are both low (ie. the Z80 INTACK signal).

6. The SYNC is clocked by the rising edge of the CPU clock.
Scope pictures (above) show this.

7. The SYNC goes low on the 16th rising clock pulse AFTER the INTACK has gone high. The SYNC (and NMI if enabled) lasts 16 clock cycles and returns high on the 16th rising clock after it went low.
Scope pictures (above) show this.

8. When enabled, the NMI is produced at the same time as the SYNC.
As measured using an oscilloscope on the ZX81.

9. VSYNC and HSYNC are "AND"ed together. If any is low then the output is held low.
As measured using an oscilloscope on the ZX81.

10. The "Mic" out is not pure - it also has the HSYNC signals in it during save (!).
The "low" signal is clean (due to point 9, above), but when the "high" pulse is generated, the HSYNCS also within it produce many glitches. The reason being that the HSYNC generation can't be turned off, and a common output pin on the ULA is used.
The output R/C circuit actually filters out most of the 15KHz sync signal, so not much appears on the output, but it is very visible on the video/cassette output pin on the ULA.
This is visible on an oscilloscope when connected to the video/cassette output on the ZX81 ULA.
The connections for my circuit shown above has split the CSYNC and the Mic output signals to clean them up. However, the behaviour in point 10, above, can be introduced with slightly different wiring if a genuine accurate signal is wanted, as shown above in the
"Alternative SYNC OUT" notes.
 


SOME OF MY OTHER PAGES

Build your own ZX80 - my page showing you how to build this old micro
   |__ ZX80 to ZX81 conversion - build the NMI generator needed to convert the ZX80 circuit into a ZX81
   |__ ZX80 software - Type in a Space Invaders game into the ZX80

Build your own Jupiter Ace - my page showing you how to build this old micro
Build your own UK101 - my page showing you how to build a greatly simplified version of this old micro
Pong - Pictures of my build of the Atari classic arcade game
My Machines - My collection of classic 80's micros

To contact me, my current eMail address can be found here. Please note that this address may change to avoid spam.